1. Field of the Invention
The present invention relates to an apparatus for storing digital data and, more particularly, to an apparatus for storing digital data which is applied to a PCM audio tape recorder or the like.
2. Description of the Prior Art
In PCM digital audio tape recorders, in general, data to be recorded is divided into a plurality of blocks every predetermined amount of the data. For example, each block comprises: a block sync signal locating at the beginning; a block address arranged at the next position; and audio data and the like located after the block address.
In the case where such a data train, divided into the blocks each having such a data constitution, is reproduced from a magnetic tape, the time base fluctuation component is included in the reproduction signal due to a variation in running speed of the magnetic tape or the like. To eliminate such a time base fluctuation component, there is used a time base correction circuit which is constituted in a manner such that the reproduction data is written into a buffer memory in response to a write clock synchronized with the reproduction signal and the data is read out of the buffer memory in response to a read clock based on a clock of a constant frequency which is generated from a crystal oscillator or the like. When the reproduction data is written into the buffer memory, the block address in the reproduction data is referred to during every block, and the data in this block is written into the address in the buffer memory which is determined by this block address. Therefore, the block address needs to be correctly reproduced. At least the block address of each block is encoded using an error detection code such as a CRC code or the like and recorded. The presence or absence of an error of the reproduced block address is checked using the error detection code. If the reproduced block address has been determined to be erroneous, the data in this block is not written into the buffer memory or written as erroneous data. An example of such a time base correction circuit has been disclosed in U.S. Pat. No. 4,398,224.
In such a conventional time base correction circuit, when the reproduction data is written into the buffer memory, it is necessary that the result of the error detection by the CRC code be known. However, the result of the error detection is unknown until all of the reproduced data of one block are obtained. Therefore, for example, as disclosed in U.S. Pat. No. 4,398,224, there are drawbacks, such that a delay circuit and a temporary memory to store at least the data of one block and a memory control circuit to control them are necessary, and a large amount of memory capacity is needed, and the circuit constitution becomes complicated.